![]() ![]() It’s not exactly areal scaling as we used to know it but it is packing more into a smaller space, so if fits the law, more or less. But it will also take place within the chips themselves with stacked transistors. This is already happening with chiplets in multi-die packages. The next step is to start stacking things. We are, notionally, already on 3nm, though the actual transistor gate is on the order of six or seven times that measurement. But the saving could be as much as 20 per cent, which few manufacturers will likely want to turn down.Īt some point you just run out of nanometres, though that might be a generation or two beyond the point where the names run out of nanometres and someone has to dream up what to call the node beyond '1nm'. ![]() The trick involves the cooperation of designers as it means the direction of routing of the first metal layer winds up being rotated 90° compared to where it would normally run. With another mask to define where these lines get cut, you can define very fine, short-distance links between neighbouring transistors that reduce the amount of space taken up by the routing. Chemical treatments use molecular-level self-alignment to form additional lines where the mask produces just one. The trick was to use the same kind of pitch splitting that made it possible to get to feature sizes way below 100nm using 193nm-wavelength light. The researchers added a level of interconnect that lies between the regular metal layers that carry many of the connections between transistors and the devices themselves. The change seems almost trivial but it relies on some smart use of lithography techniques. Things have got taller and rearranged in order to eke out every possible gain.Ī case in point is some Imec’s work described at the International Electron Device Meeting (IEDM) a couple of weeks ago. But they kept the same trend in naming to try to claim that the doubling in density with each generation was continuing. Realising that they could not make the devices smaller in the same way forever they turned to other aspects of the chip design and scaled those instead. LSI Logic was notorious for exploiting that discrepancy whenever the company named its processes to make it look as though it had stolen a jump on the competition. Technically, it was the drawn length as diffraction from the mask edges to the silicon surface made the resulting device slightly smaller. That micrometre or nanometre measurement used to mean something: the length of the gate of the smallest transistor that could be made on that node. It’s just in time as the manufacturers’ names for their process nodes have become laughably separated from reality. That last bit was something of a revision as well because the early scaling trend was more annual than biennial.įunctions, however, provide a handy get-out clause for the next few decades because scaling is not going to happen the way it used to or at least seemed to. Though Gordon Moore put some meat on the bones a decade after writing about the trend he observed in the mid-1960s when the silicon industry was just getting underway, he was careful to talk vaguely about “functions” doubling every two years. A few years later that law slammed into the wall and Intel went back to talking about transistor density. Why? The company was pushing up clock speeds in a trend allowed by another of electronics’ informal laws, devised by IBM researcher Bob Dennard in the 1970s. While it was convenient, Intel pretended that it meant compute performance. Part of that problem is that the law itself is a bit underspecified so people naturally impress their own beliefs on it. The transistor celebrated its 75th birthday on Friday (16 December), just at the point where its future is in doubt, or at least its role in the future scaling of the chips that use this now ubiquitous device.ĭepending on who you ask, Moore’s Law is in various states of disrepair. ![]()
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